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Bit
Name
Reset
Access
Description
Value
3
Mode
RELOADSTART
Description
Reload and start counter
7
DMACLRACT
0
RW
DMA Request Clear on Active
When this bit is set, the DMA requests are cleared when the corresponding DMA channel is active. This enables the timer DMA
requests to be cleared without accessing the timer.
6
DEBUGRUN
0
RW
Debug Mode Run Enable
Set this bit to enable timer to run in debug mode.
Value
0
1
Description
Timer is frozen in debug mode
Timer is running in debug mode
5
QDM
0
RW
Quadrature Decoder Mode Selection
This bit sets the mode for the quadrature decoder.
Value
0
1
Mode
X2
X4
Description
X2 mode selected
X4 mode selected
4
OSMEN
0
RW
One-shot Mode Enable
Enable/disable one shot mode.
3
SYNC
0
RW
Timer Start/Stop/Reload Synchronization
When this bit is set, the Timer is started/stopped/reloaded by start/stop/reload commands in the other timers
Value
0
1
Description
Timer is not started/stopped/reloaded by other timers
Timer is started/stopped/reloaded by other timers
2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1:0
MODE
0x0
RW
Timer Mode
These bit set the counting mode for the Timer. Note, when Quadrature Decoder Mode is selected (MODE = 'b11), the CLKSEL is
don't care. The Timer is clocked by the Decoder Mode clock output.
Value
0
1
2
3
Mode
UP
DOWN
UPDOWN
QDEC
Description
Up-count mode
Down-count mode
Up/down-count mode
Quadrature decoder mode
19.5.2 TIMERn_CMD - Command Register
Offset
0x004
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
STOP
0
W1
Stop Timer
Write a 1 to this bit to stop timer
0
START
2011-04-12 - d0001_Rev1.10
0
W1
262
Start Timer
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